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4027 Dual J-K Master/Slave Flip-Flop ic.

Product Code: CIC056
Category: IC's
Model: 4027
Brand: China
Origin: China

Discount: 0% OFF
Availability: Stock Available

4027 Dual J-K Master/Slave Flip-Flop ic.

30 TK.
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4027  Dual J-K Master/Slave Flip-Flop ic.

CD4027 belongs to the 4000 Series CMOS Logic Family of Integrated Circuits (IC’s) constructed with N- and P-channel enhancement mode transistors. CD4027 has Dual JK Master-Slave Flip-Flop

CD4027 has a supply voltage range of 5V to 20V, which is much higher than any contemporary logic family. It has buffered output which improves transfer characteristics by providing very high gain. All inputs are protected against static discharge with diodes to VDD and VSS.


CD4027 Features

  • High-Voltage Types (20V Rating)
  • Propagation Delay Time = 60ns (Typ.) at CL = 50pF, VDD = 10V
  • Standard Symmetrical Output Characteristics
  • 100% Tested for Maximum Quiescent Current at 20V
  • 5V, 10V, and 15V Parametric Ratings
  • Maximum Input Current of 1μA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
  • Noise Margin (Over Full Package Temperature Range):
    • 1V at VDD = 5V
    • 2V at VDD = 10V
    • 2.5V at VDD = 15V

    CD4027 Specifications

    Absolute Maximum Ratings

    • DC Supply Voltage Range, (VDD): -0.5V to +20V (Voltage Referenced to VSS Terminals)
    • Input Voltage Range, All Inputs: -0.5V to VDD +0.5V
    • DC Input Current, Any One Input: ±10mA
    • Operating Temperature Range: -55oC to +125oC Package Types D, F, K, H
    • Storage Temperature Range (TSTG): -65oC to +150oC
    • Lead Temperature (During Soldering): +265oC
      • At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum

      CD4027 Pinout Diagram

      CD4027 Pin Description

      Pin NoPin NameDescription
      1Q2Output Pin 2
      2Q2′Inverted Output Pin 2
      3CLK 2Clock Pin 2
      4RESET 2Reset Pin 2
      5K2Input Pin K2
      6J2Input Pin J2
      7SET 2Set Pin 2
      8VSSSupply Voltage
      9SET 1Set Pin 1
      10J1Input Pin J1
      11K1Input Pin K1
      12RESET 1Reset Pin 1
      13CLK 1Clock Pin 1
      14Q1′Inverted Output Pin 1
      15Q1Output Pin 1
      16VDDDrain Voltage

      4027  Dual J-K Master/Slave Flip-Flop ic.

      CD4027 belongs to the 4000 Series CMOS Logic Family of Integrated Circuits (IC’s) constructed with N- and P-channel enhancement mode transistors. CD4027 has Dual JK Master-Slave Flip-Flop

      CD4027 has a supply voltage range of 5V to 20V, which is much higher than any contemporary logic family. It has buffered output which improves transfer characteristics by providing very high gain. All inputs are protected against static discharge with diodes to VDD and VSS.


      CD4027 Features

      • High-Voltage Types (20V Rating)
      • Propagation Delay Time = 60ns (Typ.) at CL = 50pF, VDD = 10V
      • Standard Symmetrical Output Characteristics
      • 100% Tested for Maximum Quiescent Current at 20V
      • 5V, 10V, and 15V Parametric Ratings
      • Maximum Input Current of 1μA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
      • Noise Margin (Over Full Package Temperature Range):
        • 1V at VDD = 5V
        • 2V at VDD = 10V
        • 2.5V at VDD = 15V

        CD4027 Specifications

        Absolute Maximum Ratings

        • DC Supply Voltage Range, (VDD): -0.5V to +20V (Voltage Referenced to VSS Terminals)
        • Input Voltage Range, All Inputs: -0.5V to VDD +0.5V
        • DC Input Current, Any One Input: ±10mA
        • Operating Temperature Range: -55oC to +125oC Package Types D, F, K, H
        • Storage Temperature Range (TSTG): -65oC to +150oC
        • Lead Temperature (During Soldering): +265oC
          • At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum

          CD4027 Pinout Diagram

          CD4027 Pin Description

            Pin NoPin NameDescription
            1Q2Output Pin 2
            2Q2′Inverted Output Pin 2
            3CLK 2Clock Pin 2
            4RESET 2Reset Pin 2
            5K2Input Pin K2
            6J2Input Pin J2
            7SET 2Set Pin 2
            8VSSSupply Voltage
            9SET 1Set Pin 1
            10J1Input Pin J1
            11K1Input Pin K1
            12RESET 1Reset Pin 1
            13CLK 1Clock Pin 1
            14Q1′Inverted Output Pin 1
            15Q1Output Pin 1
            16VDDDrain Voltage

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